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Back-gated OFET Interdigitated Substrate

品牌
Sigma-Aldrich
货号
FIPMS223
规格纯度
Au source/drain, 90 nm SiO2 gate-insulator, varied W/L from 500 to 4000, 16 transistors per chip, chips (diced)
参考价格
13964 *本价格含增值税费
促销
服务
  • 原厂保证
  • 包邮
  • 增值税票
数量
-+
产品名称:
Back-gated OFET Interdigitated Substrate
产品介绍:

产品说明

一般描述

Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)
Layer structure:

  • Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3)
  • Gate oxide: 90 nm ± 10 nm SiO2 (thermal oxidation)
  • Drain/source: 30 nm Au with 10 nm high work function adhesion layer (ITO), by lift-off technique
  • Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone)
  • Layout: see images
  • Test chip size: 15 x 15 mm2
  • No. of chips: 60 per wafer
  • Contact pads: 0.5 x 0.5 mm2
  • No. of transistors: 16 per wafer

4 x transistors L= 2.5 μm W= 10 mm
4 x transistors L= 5 μm W= 10 mm
4 x transistors L= 10 μm W= 10 mm
4 x transistors L= 20 μm W= 10 mm

应用

Back-gated OFET Interdigitated Substrate (organic field-effect transistor) can be used in the fabrication of chemical sensors for potential usage in pH sensing and detection of immunoassays. It can also be used in the fabrication of biosensors by coating the sheets of the FET with a specific antibody for the detection of SARS-CoV-2. FET based biosensors can be potentially used in clinical diagnosis, point of care testing, and on-site detection.

包装

diced wafer on foil with air tight packaging

制备说明

Recommendation for resist removal:
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).

Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.

储存及稳定性

Store the wafers at a cool and dark place and protect them against sun.

Resist layer was applied to prevent damage from scratches.
Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.

法律信息

Product of Fraunhofer IPMS

产品性质

形式chips (diced)
包装pack of 1 (wafer of 60 diced chips)
储存温度15-25℃

Sigma-Aldrich

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